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可重配置处理器的体系结构级功耗模型与分析

Architecture-level power modeling and analyzing for reconfigurable processor
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摘要 按照可重配置处理器的体系结构建立并实现功耗模型;模型对处理器的电路级特性进行抽象,基于体系结构级属性和工艺参数进行静态峰值功耗估算,基于性能模拟器进行动态功耗统计,并实现三种条件时钟下的门控技术;可重配置处理器与超标量通用微处理器相比,在性能方面获得的平均加速比为3.59,而在功耗方面的平均增长率仅为1.48;通过实验还说明采用简单的CC1门控技术能有效地降低可重配置系统的功耗和硬件复杂度;该模型为可重配置处理器低功耗设计和编译器级低功耗优化研究奠定了基础。 Power model is presented and implemented according to the architecture of reconfigurable processor.The circuit char- acteristics of the processor are abstracted.Peak power is estimated based on architecture-level attribute and technology parameters. Dynamic power is computed based on performance simulator and clock gating of three conditional clocking styles is implemented. Compared with superscalar general-purpose microprocessor,reconfigurable processor can gain an average speedup of 3.59 but power is only increased by 1.48 on average.Experiment results also show that simple CC1 clock gating technology can reduce power dissipation and hardware complexity of reconfigurable system effectively.This power model is suitable for low power design and compiler optimization research of reconfigurable processor.
作者 肖玮 臧斌宇 朱传琪
机构地区 复旦大学并行处理研究所
出处 《计算机工程与应用》 CSCD 北大核心 2007年第26期34-37,40,共5页 Computer Engineering and Applications
基金 国家自然科学基金(the National Natural Science Foundation of Chinaunder Grant No60273046) 中国科学院计算技术研究所计算机系统结构重点实验室开放课题资助
关键词 可重配置处理器 体系结构级功耗模型 参数化功耗模型 动态功耗模型 低功耗优化 reconfigurable processor architecture -level power model parameterizable power model dynamic power model low - power optimization
分类号 TP302.7 [自动化与计算机技术—计算机系统结构]
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参考文献12

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二级参考文献12

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计算机工程与应用
2007年 第26期

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