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一种新型全耗尽双栅MOSFET(英文)

A Novel Fully-Depleted Dual-Gate MOSFET
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摘要 提出一种新型全耗尽双栅MOSFET,该器件具有异质栅和LDD结构.异质栅由主栅和两个侧栅组成,分区控制器件的沟道表面势垒.通过Tsuprem-4工艺模拟和Medici器件模拟验证表明,与普通双栅全耗尽SOI相比,该器件获得了更好的开态/关态电流比和亚阈值斜率.在0.18μm工艺下,开态/关态电流比约为1010,亚阈值斜率接近60mV/dec . A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第9期1359-1363,共5页 半导体学报(英文版)
关键词 异质栅 关态电流 亚阈值斜率 SOI场效应晶体管 hetero-material gate on/off current ratio sub-threshold slope SOI FET
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参考文献20

  • 1Wu Y C,Chang T C,Liu P T,et al.Reduction of leakage current in metal-induced lateral crystallization polysilicon TFTs with dual-gate and multiple nanowire channels.IEEE Electron Lett,2005,26 (9):646.
  • 2Bi Jinshun,Wu Junfeng,Hai Chaohe.Simulation of a doublegate dynamic threshold voltage fully depleted silicon-on-insulator nMOSFET.Chinese Journal of Semiconductors,2006,27(1):35.
  • 3Li Y,Chou H M.A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs.IEEE Trans Nanotechnology,2005,4(5):645.
  • 4Suzuki K,Tanaka T,Tosaka Y,et al.Scaling theory for double-gate SOI MOSFET's.IEEE Trans Electron Devices,1993,40(12):2326.
  • 5Francis P,Terao A,Flandre D,et al.Modeling of ultrathin double-gate nMOS/SOI transistors.IEEE Trans Electron Devices,1994,41(5):715.
  • 6Reddy G V,Kumar M J.A new dual-material double-gate(DMDG) nano-scale SOI MOSFET-two-dimensional analytical modeling and simulation.IEEE Trans Electron Devices,2005,4(2):260.
  • 7Chaudhry A,Kumar M J.Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET.IEEE Trans Electron Devices,2004,51(9):1463.
  • 8Goel K,Saxena M,Gupta M,et al.Three region hetero-material gate oxide stack (TMGOS) epi-MOSFET:a new device structure for reduced short channel effects.IEEE International Semiconductor Device Research Symposium,2005:72.
  • 9Zhou X,Long W.Novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology.IEEE Trans Electron Devices,1998,45(12):2546.
  • 10Zhang S,Han R,Sin J K O,et al.Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD.IEEE Trans Electron Devices,2002,49(8):1490.

二级参考文献25

  • 1Wong H S P,Frank D J,Solomon P M,et al.NanoscaleCMOS.Pro IEEE,1999,87:537
  • 2Iwai H,Momese H S,Satio M,et al.The future of ultra-small-geometry MOSFETs beyond 0.1 micron.Microelectron Eng,1995,28:147
  • 3Iwai H.CMOS technology-year 2010 and beyond.IEEE JSolid-State Circuits,1999,34:357
  • 4Fiegna C,Iwai H,Satio W T,et al.Scaling the MOS transistor below 0.1μm:methodology,device structures,and technology requirements.IEEE Trans Electron Devices,1994,ED-41:941
  • 5Hori A,Mizuno B.CMOS device technology toward 50nm region--performance and drain architecture.In:IEDM Tech Dig,1999:641
  • 6Timp G,Bourdelle K K,Bower J E,et al.Progress toward 10nm CMOS Devices.In:IEDM Tech Dig,1998:615
  • 7Ono M,Saito M,Yoshitomi T,et al.A 40nm gate length n-MOSFET.IEEE Trans Electron Devices,1995,ED-42:1822
  • 8Chung J,Jeng M C,Joon J E,et al.Deep-submicrometer MOS devices fabrication using a photoresist-ashing technique.IEEE Electron Device Lett,1998,9:186
  • 9Horstmamm J T,Hilleringmann U,Goeser K F.Matchinganalysis of deposition defined 50-nm MOSFET's.IEEE Trans Electron Devices,1998,ED-45:299
  • 10Wakabayashi H,Ueki M,Narihiro M,et al.45nm gate length CMOS technology and beyond using steep halo.In:IEDM Tech Dig,2000:49

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