10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现

Realization of 10bit, 200MHz sampling frequency CMOS video D/A converter with gradient error compensation

提出了一种10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现电路。采用分段式结构,利用层次式对称开关序列消除由热分布不均所引起的对称误差。该DAC集成在一款视频自适应均衡芯片中,整个芯片采用Charted 3.3V电压、0.35μm CMOS工艺生产制造。DAC的面积为1.26mm×0.78mm,工作在4Fsc(14.318MHz)采样频率时,其有效数据比特为9.3个,其积分非线性误差和微分非线性误差均小于±0.5LSB。

A circuit of 10bit, 200MHz sampling frequency current steering DAC with hierarchical symmetrical switching sequences was presented, which compensate the gradient error. The DAC employs segmented architecture. An integral linearity error caused by error distributes of current sources was reduced by a new switching sequence called ＂hierarchical symmetrical switching＂. The DAC was built in a video-rate adaptive equalizer IC, which was fabricated in a 0.35μm, 3.3V CMOS process. The area of DAC is 1.26mm× 0.78mm. When operating at 14.318 MHz （4Fsc） sampling freguency, the effective numbers of bits is 9.3. Both the integral and the differential linearity errors are less than ± 0.SLSB.