基于并行结构分布式算法的FIR滤波器设计

Design of FIR Filter Based on Distributed Algorithm with Parallel Structure

本文详细地叙述了线性相位FIR数字滤波器的一种设计方法。首先通过MATLAB设计出一个具体指标的FIR滤波器,并对滤波器系数进行了处理,使之便于在FPGA中实现。在滤波器硬件设计中,采用了分布式算法来计算滤波器中的乘积和运算,提高了信号的处理效率。由于采用了分布式算法的并行结构,提高了滤波速度。本论文用VHDL编写代码,用MaxplusII进行编译、综合和仿真,FPGA器件选用ALTERA公司的FLEX10K系列7万门的芯片。最后,对设计结果做了验证,验证结果表明:这种方法大大减少了FPGA硬件资源的耗费,所设计的滤波器运算正确,实现了快速滤波功能。

A design method of FIR digital filter with linear phase is fully presented. First, a specific FIR filter is designed using MATLAB. In order to realize the filter with FPGA device successfully, its coefficients are well handled. In hardware design, the distributed algorithm （DA） is used to calculate the sum of products in the filter, which enhances the signal processing efficiency. And in order to accelerate the speed of the filter, parallel structure of DA is adopted. The FIR filter in this paper was coded with VHDL, compiled, synthesized and simulated with Altera Maxplus Ⅱ. FLEX10K70 （70000 gates） from Ahera was selected as the hardware of the filter. Lastly, the designed filter was tested and verified. Simulation result shows that the proposed design method saves the resources in FPGA greatly; the designed filter operates correctly and realizes the function of high speed filtering.