基于FPGA的E1接口误码测试方案

The Error Code Test Scheme of E1 Interface Based on the FPGA

基于现场可编程门阵列(FPGA)的E1接口的误码测试方案分为发送和接收两个模块,主要优势在于可以测试单向信道的误码情况。由于伪随机序列的可重复产生以及0、1等概的特性,故发送端可采用此类序列,该文选用m序列作为发送序列,并且通过插入同步码元,作为接收端同步测试。在接收端用同样的m序列产生器,通过时钟提取模块,产生相同的本地序列。本地序列和接收序列相比较,就可以检测到误码。

Here we put forward the test scheme of E1 on the basis of FPGA. It includes two parts： transmitting and receiving. The advantage of this scheme is that it can test the error code rate of the single channel. It is just the case of setting the sending and receiving equipment in the different places. Due to the characteristics of duplicated producing of the PN sequence, here we use this sequence in the sending end. Usually the PN code in the transmitting end is using m series. So in the receiving end using the same arrangemsat transmitting end does and controlled by the synchronization signal, producing the same loacl arrange meat. The local arrange ment is compared with the receiving arrangment, and the goal is reachcy --testing the rate of the error code.