6SCHLICHTMANN U. Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today [ C ]//Proceedings of the International Symposium on Quality Electronic Design. San Jose : [ s. n. ] ,2002:225.
7SIVA N, VIVEK D, RON W. Process Variation: Is It too Much to Handle? [ C ]//Proceedings of The International Symposium on Quality Electronic Design. San Jose, California:[s. n. ] ,2002:213.
8DOONG K Y Y. Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site test structures(AFS-TS) [J]. Proceedings of SPIE,2002,4692 (7) :81-87.
9KHARE J B. Extraction of defect size distributions in an IC layer using test structure data [ J ]. IEEE Transactions on Semiconductor Manufacturing, 1994,8 ( 7 ) : 354-368.