CMOS2.5 Gb/s时钟恢复电路设计

A Design of CMOS Clock Recovery Circuit in 2.5 Gb/s

设计采用0.35μm CMOS工艺来实现一款CMOS2.5 Gb/s时钟恢复电路。由于0.35μm CMOS工艺的限制,采用了预处理电路加锁相环的电路结构。这种电路结构有利于单片集成且工作速度高。预处理器主要有延迟单元、乘法器和窄带滤波电路构成,可以从NRZ数据中得到时钟信号。锁相环采用二阶的模拟锁相环结构,鉴相器采用Gilbert乘法器,环路滤波器采用无源滤波器,VCO采用3级环形振荡器。

The CMOS clock recovery circuit in 2.5 Gb/s is designed by 0.35 /;m CMOS technology. Because of the limitation of the 0.35 μm CMOS technology,we employ a full analog structure which is composed of a preprocessor and a Phase - Locked Loop（PLL）. This kind of circuit can wok at high speed. The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow - band filter. The analog PLL contains three basic components： a Gilbert multiplier PD,a passive filter and a three- stage ring oscillator.