面向存储系统的低功耗SoC设计

Low Power Design for SoC Storage System

降低存储系统功耗是SoC设计中的重要问题,基于对程序执行与器件特性的分析,在SDRAM中引入数据缓冲区,给出针对多进程数据访问特性的实现方法,降低了程序运行时外存设备的功耗。在EMI中实现了指令FIFO,并给出定制方法,降低了程序运行时的SDRAM能耗。实验与仿真表明,该方法能有效降低程序运行时SoC存储系统整体功耗。

Reducing the power of storage system is an important goal in SoC design. Based on the analyses of program and device, this paper proposes a method for this goal. This method introduces data buffer in SDRAM in order to reduce the power of external memory in the environment of multi-process and instruction FIFO in EMI is implemented in order to reduce the energy consumed by SDRAM when program is running. Results of experiment and simulation showed that this method can reduce the overall power of SoC storage system when program is running.