采用多输入浮栅MOS器件的四值编-译码电路设计

Quaternary Encoder and Decoder Circuits Using Multiple-input Floating-gate MOS Transistors

提出一种采用多输入浮栅MOS管设计具有可控阈值功能的电压型多值逻辑电路的方法.对每个浮栅MOS管的逻辑功能均采用传输开关运算予以表示以实现有效综合。在此基础上提出了一种新的电压型多输入浮栅MOS四值编码器和译码器设计。所提出的电路在结构上得到了非常明显的简化,并可采用标准的双层多晶硅CMOS工艺予以实现。此外,这些电路具有逻辑摆幅完整、延迟小等特点。采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性。

A design method for voltage-mode multiple-valued logic （MVL） circuits using multiple-input floating-gate MOS（FGMOS） transistors with threshold-controllable function was presented. The logical relation of each floating-gate MOS transistor was formulated by using the transmission operation in order to make effective and practical use of the circuits. By employing the voltage-threshold controlling technique, novel voltage-mode quaternary encoder and decoder using multiple-input floating-gate MOS transistors were designed. The important advantages of the proposed circuits are that they can be implemented by a standard double-polysilicon CMOS process, and are considerable simpler configuration than previously reported ones. Furthermore, they have some other favorable properties including full logic swing and low propagation delay. From the HSPICE simulation results using TSMC 0.35μm double-polysilicon CMOS technology, the effectiveness of the proposed approach is validated.