基于脉动阵列的FIR滤波器设计

FIR Filter Design Based on Systolic Array

为了提高FIR滤波器的运算速度,把脉动阵列的处理器结构和FIR滤波器相结合,设计了高效的FIR滤波器。该结构具有模块化、规则性和高度流水的特点。在FPGA上验证,实验结果表明,该设计达到了较高的运算速度,可以满足数字信号处理中高效、实时的要求。而且该结构易于扩展,可实现任意阶的FIR滤波器。

In order to increase FIR processing speed, the FIR filter of systolic array structure is designed. It has the characteristic of modularization, regulation and highly pipelining structure,and using FPGA resource well. Experimentation result indicates that it has reached upper processing speed, could satisfy high efficiency and real - time request in digital signal processing. This structure can extend easily,realize FIR filter of any stairs.