一种新型低功耗触发器的设计

Design of Novel Low Power Flip-flops

介绍一种新型低功耗触发器的设计方法,这种新型的双门控触发器克服了原门控触发器只有在输入信号跳变比较慢或基本不跳变时才满足低功耗要求的局限性.这种双门控的触发器可以用于原门控触发器所适用的所有低功耗电路或标准单元库的设计.

A novel low power flip-flop is presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitic show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.