基于CPLD的倒数计数器

CPLD-based Design for Measuring Low Frequency

用VHDL在CPLD器件上实现一种数字频率计测频系统,能够用十进制数码管显示被测信号的频率及其他多种物理量.整个频率计设计在1块CPLD芯片上,与其他方法做的频率计相比,具有体积小、可靠性高、功耗低的特点.

Direct-reading and amount of error are always in conflict with each other in measuring low frequency. In this article, it adopts a ＂count-down＂ design method to solve this collision, A digital frequency measure system can be implemented using VHDL in the CPLDs, and this system can demonstrate the measured frequency in the form of decimal system. Other than the frequency, the proposed system can also measure many other physical signals. The whole cymometer is designed on a CPLD and embedded with a decimal system, Compared with other existing cymometers, the proposed system is smaller in volume, more reliable in functioning and lower in power consumption.