一种QPSK位同步电路的设计

The Design of Interpolation-based QPSK Symbol Timing Synchronization Circuit

本文针对QPSK调制信号,提出了一种立方内插、预滤波和Gardner定时误差检测相结合实现符号位同步的电路结构。在Matlab的AlteraDSPBuilder环境下实现该算法的设计,并进行功能仿真,最后在AlteraStratixII开发板上FPGA实现了该算法。此电路已用于实际的接收机中,工作时钟频率最高可达到130MHz,能够纠正0.1%的定时误差,性能良好。

In this paper,a circuit structure for symbol synchronizing is proposed,which is based on Cubic Interpolate ,Pre-fiher and Gardner TED.This loop is builded with Altera DSP Builder in Matlab and is implemented in Altera StratixⅡ FPGA board.This ciruit is used in an practical receiver,which can be corrected 0.1% symbol Timing error,work at clock rate up to 130MHz,and can work stably, has good performce.