一种基于预比较的低功耗高速缓存设计

Design of a Low-Power Cache with Partial-Tag Comparison

介绍了一种采用预比较方法的高速缓存结构。通过标志段的预比较来避免对无关标志段和数据段的访问以降低访问功耗。并引入反相时钟来优化其访问时序,使平均访问延时少于一个周期。实验显示,在保持命中率的基础上,对测试程序的访存优化表现出很好一致性,且功耗优势随相联度增加而增大。相比预测型结构,在8路相联度下平均有28.5%的功耗降低。

a novel cache structure with partial tag comparison is presented. By trigging the partial comparison first, power consumption on unrelated tag and data bank can be saved. Meanwhile, inversed clock is applied to optimize the access sequence, leaving the average access delay less than one cycle. Simulation shows that the proposed structure, which maintains the cache hitrate, has good consistency on variant benchmarks, and its power advantage increases under higher set associativity. Compared to predictive cache under 8 way associativity, it achieves 28.5% power reduction in average.