数字延迟锁定环设计技术研究

Research on Digital Delay-locked Loop Design

数字延迟锁定环(DLL)可以产生精确的延迟效果而基本不受工艺、电源和温度等影响,常用来生成稳定的延迟或多相位的时钟信号。该文利用D触发器实现鉴相,给出了一种简洁新颖的数字电路技术的延迟锁定环(DLL)的设计方法。模拟结果表明:该DLL在工作频率范围内支持0°～360°相移,从复位到稳定的时间为2 688个参考时钟周期。在0.35μm SMIC digital CMOS工艺模型下,鉴相精度达到200ps,工作频率范围在23MHz～200MHz。该电路还具有可编程特性。

DLL may generate an accurate delay which is rarely affected by P.V.T conditions, so it is used to generate stable delay or multi-phase clocks. A novel method of digital delay-locked loop is addressed, which utilizes a flip-flop to detect a phase difference. Simulation indicates that 0°~360° phase shift is supported and its locking time, since reset, is 2 688 reference clocks. Under the 0.35μm SMIC digital CMOS process, the precision reaches 200ps and the supported frequency range spans from 23MHz to 200MHz. The programming feature is also available, which facilitates the use of specifying specific delay.