芯片粘接空洞对功率器件散热特性的影响

Effect of Adhesive Void on Heat Diffusion Performance of Power Chip

芯片粘结层的空洞是造成功率半导体芯片由于散热不良而失效的主要原因。运用有限元法对芯片封装结构进行了热学模拟分析,研究了粘结层材料、粘结层厚度、粘结层空洞的面积、空洞的位置对芯片温度分布以及芯片最高温度造成的影响。对标准中规定应避免出现的粘结状况进行了分析,研究结果表明空洞的面积越大,芯片的温度越高。空洞位于拐角,即粘结区域四角的位置时,芯片散热情况最差。而在标准中给出的,芯片空洞面积达50%,且位于拐角时,芯片的温度最高。

Adhesive void is the main reason for the heat diffusion failure of power semiconductor chip.Thermal analysis on chip packaging structure was carried out based on FEM（finite element method）.Effect of adhesive layer material,layer thickness,adhesive void area and void position on temperature distribution and the maximum temperature were studied.Adhesive conditions that should be avoided were analyzed.Results show that the temperature of the chip will increase with the void area increasing.The worst heat diffusion condition is that the voids distribute at the four corners of adhesive zone.In the standard,the highest chip temperature appears when total void area reaches 50%,and all at the corners of the adhesive zone.