层次化的片上网络设计方法

Hierarchical Network-on-Chip Design Method

半导体技术的发展以及系统芯片应用复杂度的不断增长,使得片上互连结构的吞吐量、功耗、信号完整性、延迟以及时钟同步等问题更加复杂,出现了以片上网络为核心的通信结构。由于系统芯片结构和片上通信的固有特性,从提高通信性能和降低硬件开销的角度进行层次化片上网络的设计对系统芯片的发展具有重要意义。本文提出了层次化的片上网络设计方法,根据实现工艺和应用需求,进行层次划分,产生若干个IP子集(将这个子集称为"簇"),按照簇间的通信需求进行片上网络的设计。实验表明,采用层次化的片上网络设计方法,能够有效提高系统性能,降低硬件实现的开销,同时满足一定的服务质量要求。

With the development of VLSI technology and increasing complexity of System-on-Chip applications, on-chip communication architecture design encounters some problems, such as throughput, power, signal integrity, latency and clock synchronization, Network-on-Chip （NoC） was introduced. With on-chip communication＇s specific pattern, it is of great significance to design hierarchical Network-on-Chip to improve communication performance and reduce hardware cost, This paper puts forward a hierarchical NoC design method. According to the technology and application requirements, researchers can generate several IP core subsets （＂cluster＂）, and design a NoC architecture as inter-cluster communication requirements. Experiments show with hierarchical NoC design method, this method can improve system performance efficiently, decrease hardware cost, and meet Quality-of-Service requirements at the same time.