基于数据采集的VHDL带通滤波

Using VHDL to Build the Band-pass Filter Based-on Data Acquisition System

针对纯硬件实现RC带通滤波具有很大的局限性,而HDL(硬件描述语言)具有高层次的自上而下的设计方法,为系统硬件设计提供了更大的灵活性,具有更高的通用性,能有效地缩短设计周期,减少生产成本[1]。文中简要介绍了一种VHDL实现通带为0.1s-0.4s的时域带通滤波器,该滤波器主要用于预处理数据位流,该数据位流是由同步数据传输延时补偿网络采集到的。为便于利用计算机进行1.5μs在线时序仿真,文中给出了通带为0.1μs-0.4μs的时域等效带通滤波时钟的VHDL设计实例,并利用时序矢量仿真波形初步分析了抖动容限[2],从而证实了该实例的正确与合理性。

Realizing the RC band - pass filter by pure hardware has a very big limitation, but HDL （ hardware description language） is a top - down design method of high - level hierarchy ,which has provided higher flexibility and higher versatility for the system hardware design, and it can effectively shorten the design cycle, and reduce the production cost . Therefore , this paper introduces a method of using VHDL （Very High Speed Integrated Circuit Hardware Description Language） to build the band - pass filter in time - region whose bandwidth is between 0. 1 second and 0.4 second based - on data acquisition system. It is mainly used for pre - processing data bits - streams which is acquired by the synchronous data transmission delay - compensated system. In order to do the computer online vector wave - simulation of timing - sequence and analyze the validity and rationality of its jitter - tolerance result in 1.5μs logically, the paper gives a design example with VHDL code of the equal filter clock of the band - pass filter in time -region whose bandwidth is between 0. 1μs and 0.4μs.