摘要
采用VHDL语言,在FPGA上实现了单精度浮点除法器的设计,通过采用SRT算法、SD表示法、常数比较法以及飞速转换法,进一步提高电路的运算速度。使用NC-sim和Maxplus2仿真软件进行前仿真和后仿真,使用Synplify进行逻辑综合,采用EPF10K40RC208-3芯片,对除法器进行了仿真。
Using VHDL,a single-precision-floating divider is designed on a FPGA Chip,The operating speed is much further increased by using four methods-SRT algorithm,SD representation,Contant Comparison and Flying Transition.In the article,the presim and the post-sim based on EPF10K40RC208-3 is conducted by using the simulation software-NC-sim and Maxplus2,and the logic synthesis is conducted by using Synplify software.
出处
《电子技术应用》
北大核心
2007年第10期56-58,62,共4页
Application of Electronic Technique
关键词
除法器
SRT
单精度浮点
数字循环法
仿真
Divider
SRT
Single Precision Floating
Digital Loop Method
Simulation
