摘要
A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television （HDTV） system-on-a-chip （SoC） platform, especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property （IP）, the interrupt controller has reusability and expandability with the layered structure.
