基于混合架构的H.264/AVC视频编码器设计

Design of H.264/AVC Video Coder Based on Mixed Architecture

提出了基于DSP+FPGA混合平台的H.264/AVC编码器设计思路与实现方法。以DSP为主处理器,FPGA为协处理器实现算法的硬件加速,针对编码器中最复杂耗时的模块,设计相应的硬件加速引擎。并针对硬件加速引擎制定出便于控制和数据传输的软/硬件通信协议,实现了H.264/AVCD1编码器所需的实时性能。

A design and implementation method of H.264/AVC encoder based on mixed structure is introduced, in which DSP is used as a main processor and FPGA as an assistant processor to accelerate arithmetic by hardware. In order to meet required real-time performance, hardware engine is designed for the most complicated and time-consuming module. According to the engine, it constitutes a software and hardware communication agreement, which makes control and data transporting easily, and realizes the real-time performances which H.264/AVC D1 coder needs.