期刊文献+

边界约束下的增量式布图规划算法

Incremental floorplanning algorithm with boundary constraints
原文传递
导出
摘要 快速地在局部范围内调整布图已经成为一种设计需要。该文提出了一种二阶段法来实现边界约束下的增量式布图规划算法。根据已有布图规划建立松弛推移图,直观描述各模块之间"空白区"和松弛量的情况;同时建立模块交换图,记录所有具有形状相似特征的模块集合,基于这2个图进行增量式布图规划。第1阶段,基于推移图和交换图调整布图规划,使其满足边界约束。第2阶段,再次利用交换图进行互连性能优化。实验结果表明该算法在较短的时间里不仅对原有布图规划进行了有效调整满足了给定的所有的几何约束,而且还保证了芯片的面积和线长效果。 Quick incremental local floorplan modifications are becoming necessary with new developments in technology. This paper introduces a two-stage strategy to solve the incremental floorplanning problem with boundary constraints. The algorithm first builds the slack push graph and module exchange graph according to the initial floorplan. The slack push graph describes the dead spaces between any blocks and the slack push distance for each module. The module exchange graph identifies those modules having the same size characteristics. The algorithm uses these two graphs to satisfy the boundary constraints and then optimizes the design using the module exchange graph. The algorithm satisfies all boundary constraints while maintaining total area and wire length.
出处 《清华大学学报(自然科学版)》 EI CAS CSCD 北大核心 2007年第10期1685-1688,共4页 Journal of Tsinghua University(Science and Technology)
基金 国家自然科学基金资助项目(90407005 60473126)
关键词 超大规模集成电路 增量式布图规划 边界约束 松弛推移图 模块交换图 VLSI incremental floorplanning boundary constraints slack push graph (SPG) module exchange graph (MEG)
  • 相关文献

参考文献7

  • 1HONGXianlong,MAYuchun,DONGSheqin,CAIYici,Chung-KuanCheng,GUJun.Corner block list representation and its application with boundary constraints[J].Science in China(Series F),2004,47(1):1-19. 被引量:3
  • 2Young F Y, Wong D F, Yang H H. Slicing floorplans with boundary constraints [J]. IEEE Transactions on CAD, 999, 18(9): 1385-1389.
  • 3Cong J, Sarrafzadeh M. Incremental physical design [C]// Proceedings International Symposium on Physical Design, San Diego, CA, USA, 2000.- 84-92.
  • 4Creshaw J, Sarrafzadeh M, Banerjee P, et al. An incremental floorplanner [C]// Proceeding of IEEE, Great Lakes Sym on VLSI, MI, USA, 19997 248-251.
  • 5LI Zhuoyuan, WU Weimin, HONG Xianlong. Incremental placement algorithm for multi-objective optimization [C]// ASIC, 2003. Proceedings 5th International Conference, Beijing, 2003, 1: 178-182.
  • 6YANG Liu, DONG Sheqin, HONG Xianlong, et al. A novel incremental algorithm for non-slicing floorplan with low time complexity [C]// JCIS CSI, Salt Lake City Marriott-City Center, Salt Lake City, Utah, USA, 2005: 241- 244.
  • 7HONG Xianlong, DONG Sheqin, GANG Huang, et al. Corner block list representation and its application to flooplan optimization [J]. IEEE Transactions on Circuits and Systems, II, 2004, 51(5): 228-233.

二级参考文献18

  • 1[11]Ma Yuchun, Hong Xianlong, Dong Sheqin et al., VLSI floorplanning with fixed topology, Microelectronics(in Chinese), 2000, 30: 22-24.
  • 2[12]Young, E Y., Wong, D. F., Yang, H. H., Slicing floorplans with preplaced modules, in Proc. IEEE Int. Conf.Computer-Aided Design, 1998, 252-258.
  • 3[13]Murata Hiroshi, Fujiyoshi Kunihiro, Kaneko Mineo, VLSI/PCB placement with obstacles based on sequence pair, in IEEE Trans. on Computer Aided Design, 1998, 17( 1): 60-67.
  • 4[14]Young, F. Y., Wong, D. F., Slicing floorplans with range constraint, in Proc. Intl. Symp. on Physical Design(ISPD99) (ed. IEEE), 1999, 97-102.
  • 5[15]Young, F. Y., Wong, D. F., Yang, H. H., Slicing floorplans with boundary constraints, in IEEE Trans. on Computer Aided Design, 1999, 18(9): 1385-1389.
  • 6[16]Kang, M., Dai, W. M., General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure, in Proceedings of IEEE Asia and South Pacific Design Automation Conference(ASP-DAC97) (ed. IEEE), 1997, 265-270.
  • 7[17]Huang, G., Hong, X. L., Qiao, C. G. et al., A timing driven block placer based on sequence pair model, in Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC99) (ed. IEEE), 1999,249-252.
  • 8[18]Nagao, A., Shirakawa, I., Kambe, T., A layout approach to monolithic microwave, IEEE Trans. on Computer Aided Design, 1996, 17(12): 1262-1272.
  • 9[1]Lauther, U., A min-cut placement algorithm for general cell assemblies based on a graph representation, in Proceedings of 16th ACM/IEEE Design Automation Conference (DAC79) (ed. ACM, IEEE), 1979, 1-10.
  • 10[2]Dai, W. M., Eschermann, B., Kuh, E. S. et al., Hierarchical placement and floorplanning in BEAR, in IEEE Trans. on Computer Aided Design, vol. CAD-8, 1989, ( 12): 1335- 1349.

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部