期刊文献+

一种改进的电压按比例缩放式数模转换器的架构 被引量:1

A New Framework of Voltage Scaling DAC
下载PDF
导出
摘要 数模转换器是数字电子系统和模拟电子系统之间的常用接口电路。典型电压按比例缩放式结构的数模转换器可保证输出的单调性。分析典型的电压按比例缩放型数模转换器的工作原理,提出一种改进架构,从而降低了集成电路的制造成本。 The DAC is often used as input/output circuit of digital electronic system and analog electronic system. In the front and the end of the advanced electronics system, digital to analog converters (D/A converters) are applies to improve the performance of the digital processing technique. The representative voltage scaling DAC have the monotonic property of output. At first, I analyze the working theory of voltage scaling DAC, and then bring forward a new framework. It also has the monotonic property of output. It reduces the number of resistance and simulate switch. It retrenches the area of layout observably and reduces the working-cost of IC. The number of 8-bits voltage scaling DAC’s resistance reduces from 256 to 16.
作者 应建华 郑强
出处 《计算机与数字工程》 2007年第10期134-135,共2页 Computer & Digital Engineering
关键词 数模转换器 电压按比例缩放 版图 DAC,voltage scaling,layout
  • 相关文献

参考文献3

  • 1James Caffrey.了解D/A转换器的架构[J].今日电子,2003(11):4-5. 被引量:1
  • 2Phillip E.Allen.CMOS模拟集成电路设计[M].(第二版),北京:电子工业出版社,2005
  • 3毕查德·拉扎维.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2002.

共引文献33

同被引文献12

  • 1Wei Baolin, Dai Yujie, Zhang Xiaoxing, et al. A 2.4- GHz low-if front-end receiver in 0. 18-1xm CMOS for IEEE 802. 15.4 WPAN Applications [ C]//1EEE 8th International Conference on AS1C. Changsha, China, 2009:1137 - 1140.
  • 2Cheng Kuang-Wei, Natarajan K, Allstot D. A 7.2 mW quadrature GPS receiver in 0. 13 txm CMOS[C]//IEEE International Solid-State Circuits Conference. San Francisco, USA, 2009: 422- 423, 423.
  • 3Mostafanezhad I, Boric-Lubecke O, Lubecke V. A coherent low IF receiver architecture for doppler radar mo tion detector used in life signs monitoring [ C ]//IEEE Radio and Wireless Symposium. New Orleans, USA, 2010:571-574.
  • 4Khumsat P, Worapishet A. 5th-order chebyshev active- RC complex filter employing current amplifiers [ C ]// International Symposium on Integrated Circuits. Singapore, 2007 : 281 - 284.
  • 5Pu Young Gun, Jung Sung Kyu, Park DoJin. A CMOS baseband complex bandpass filter with a new automatic tuning method for PHS applications[ C ]//The 33 rd European Solid-State Circuits Conference. Munich, Germany, 2007:500-503.
  • 6Oskooei M S, Masoumi N, Kamarei M. A 4. 35-mW + 22-dBm HP3" continuously tunable channel select filter for WLAN/WiMax receivers in 90-nm CMOS [ C ]// IEEE Radio Frequency Integrated Circuits Symposium. Anaheim, USA, 2010 : 517 - 520.
  • 7Hu Jin, Hei Huage, Liu Qingbo, et al. CMOS 4th-order gm-c low-pass filter with wide tuning range in high frequency [C ] // IEEE 8th International Conference on ASIC. Changsha, China, 2009 : 277 - 279.
  • 8Crombez P, Craninckx J, Steyaert M. A 100 kHz - 20 MHz reconfigurable nauta Gm-C biquad low-pass filter in 0. 13um CMOS [C]//IEEE Asian Solid-State Circuits Conference. Cheju Island, South Korea, 203q: 444- 447.
  • 9Fan Jinhan, Li Wei, Li Ning, et al. A 260 MHz 5th- order gm-c biquad low-pass filter with wide frequency tuning range [ C ]//The 9th International Conference on Solid-State and Integrated-Circuit Technology. Beijing, China, 2008 : 1617 - 1620.
  • 10Nauta Bram. Analog CMOS filters for very high frequencies[M]. Norwell, USA : Kluwer Academic Publishers, 1993:85 - 160.

引证文献1

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部