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一种高性能的H.264变换编码IP设计

A High-Performance Transform Coding IP Design for H.264
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摘要 H.264是ITU与ISO联合共同开发的具有高编码效率、高压缩质量的视频新标准。H.264采用了4×4块的无乘法整数变换编码算法,有效地降低了编解码的运算量,且避免了反变换的误匹配问题。文章通过详细分析H.264的整数DCT变换及Hardmard变换的算法,提出了一种高性能的变换编码的硬件IP设计,通过Modlesim仿真和DC综合能较好地达到预先设计要求。 H.264 is the new video coding standard established by ITU and ISO, which has high coding efficiency and high compres-sion quality. The 4×4 transforms in H.264 can be computed exactly in integer arithmetic without multiplication, thus minimizing computational complexity and avoiding inverse transform mismatch problems. This paper proposes a high-performance transform coding IP design with a detailed analysis on the algorithm of the integer DCT transform and Hardmard transform, and the result of simulation by Modlesim and synthesis by Design Compiler shows that this system meets the design requirement.
出处 《信息通信》 2007年第5期30-32,共3页 Information & Communications
关键词 H.264 整数DCT变换 Hardmard变换 IP设计 H.264 Integer DCT transform, Hardmard transform, IP Design
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参考文献6

  • 1[1]Kuan-Hung Chen,Jiun-In Guo,Member,and Jinn_Shyan Wang," A High-Performance Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264",IEEE Transactions on Circuits and Systems for video technology,vol.16.no.4.April 2006
  • 2[2]T.Wiegand,and G.Sullivan,Draft ITU-T recommendation and final draft international standard of joint video specification,ITU-T rec.H.264[ISO/IEC 14496-10AVC,available:ftp://ftp.imtc-files.org/jvt-experts
  • 3[3]H.S.Malvar,A.Hallapuro,M.KaracZewicz,and L.Kerofsky," Low-Complexity Transform and Quantization in H.264/AVC," IEEE Transactions on Circuits and Systems for video technology,vol.13,no.7,July 2003
  • 4[4]I.E.G.Richardson," H.264/MPEG-4 Part 10:Overview," www.vcodex.com.20/12/2002
  • 5[5]R.Kordasiewicz and S.Shirani,"Hardware implementation of the optimized transform and quantization blocks of H.264," in Proc.Canadian Conf.Electr.Comp.Eng.,vol.2,May2004,pp.943-946
  • 6[6]L.Z.Liu,Q.Lin,M.T.Rong,and J.Li,"A 2-D forward/inverse integer transform processor of H.264 based on highly-paralled architecture," in Proc.4th IEEE Int.Workshop on System-on-chip for Real-Time Applications (IWSOC'04)

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