多端口存储器控制器IP核的设计与实现

Design and Implementation of Multi-Port Memory Controller IP Core

提出了一种通用的多端口存储器控制器的设计与实现方案,该方案采用AMBA(advanced microcon-troller bus architecture)总线,最多可支持6个AHB(advanced high-performance bus)主设备同时访问存储器;支持包括SRAM、ROM、NOR-FLASH、SDR-SDRAM、DDR-SDRAM在内的多种存储器;内部设计实现的仲裁器采用固定优先级和TimeOut机制相结合的仲裁策略.基于SMIC 0.13μm CMOS工艺库,芯片面积约为230653μm2,系统时钟为130 MHz.FPGA验证结果表明:该方案实现的存储器控制器能够充分利用存储器的带宽,提高系统的性能.

An implementation scheme for multi-port memory controller was proposed. This controller can support six AHB interfaces for accessing external memory, support SRAM, ROM, NOR-FLASH, SDR-SDRAM and DDR-SDRAM. The arbiter in it uses fixed priority combined with timeout arbitration strategy. Based on the SMIC 0.13 μm standard cell library, area of the chip is about 230653 μm^2 , system clock is 130 MHz. FPGA simulations show that the implementation scheme can improve system performance significantly.