期刊文献+

基于模拟退火方法的多级时钟树的构建 被引量:2

Construction of Multi-level Clock Tree Based on Simulated Annealing
下载PDF
导出
摘要 在时钟布线中,时钟信号和时钟偏差对电路性能的影响越来越明显。针对传统的时钟网络拓扑生成算法存在的不足,提出了时钟二叉树的"多级"模型并设计了基于模拟退火方法的时钟二叉树形成算法。用该算法对随机测试例子和标准标杆测试例子的测试中发现,较之传统的启发式算法,该算法能产生更好的测试结果。 In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance. Due to the shortcomings of traditional topology construction algorithm for clock network, multi-level model of clock binary tree and binary tree construction algorithm of clock signal based on simulated annealing are presented. The test results for random test cases and standard benchmark test cases by this algorithm show that this algorithm can produce much better test results compared with traditional heuristic algorithms.
出处 《计算机工程》 CAS CSCD 北大核心 2007年第20期1-3,7,共4页 Computer Engineering
基金 中国博士后科学基金资助项目(2005038151)
关键词 二叉树 时钟布线 模拟退火 多级模型 binary tree clock routing simulated annealing multi-level model
  • 相关文献

参考文献5

  • 1Jackson M A B, Srinivasan A, Kuh E S. Clock Routing for High-performance ICS[C]//Proc.of ACM/IEEE Design Automation Conference.1990,573-579.
  • 2Kahng A B, Cong J, Robins G High-performance Clock Routing Based on Recursive Geometric Matching[C]//Proc.of ACM/IEEE Design Automation Conference.1991,322-327.
  • 3Tsay R S, Exact Zero Skew[C]//Proc. of IEEE International Conference on Computer-aided Design.1991,336-339.
  • 4Rubinstein J, Penfield R Horowitz M A. Signal Delay in RC Tree Networks[J]. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1983,2(3):202-211.
  • 5Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho Routing with Minimum Wavelength[J] Circuits and Systems II: Analog and Digital 39(11):799-814.et al.Zero Skew Clock IEEE Transactions on Signal Processing,1992,

同被引文献16

  • 1刘德启,胡忠.深亚微米SOC芯片分层设计方法[J].半导体技术,2007,32(4):335-338. 被引量:1
  • 2O. OMEDES. A flexibility aware budgeting for hierarchical flow timing closure[C]//San Jose, CA, USA: IEEE/ACM International conference on Computer-aided design, 2004 : 261-266.
  • 3S. Ghiasi, E. Bozorgzadeh, Po-Kuan Huang, et al. A Unified Theory of Timing Budget Management [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006,25 (11) : 2364-2375.
  • 4杨磊.龙腾S2的数据通路优化[D].西安:西北工业大学,2008.
  • 5Cadence Design Systems. Encounter Foundation Flows: Hierarchical Implementation Flow Guide[R]. Cadence, 2009.
  • 6J. Rabaey, A. Chandrakasan, B. Nikolic. Digital integrated circuits., a design perspective[M].北京:电子工业出版社,2004:362-366.
  • 7L. Singhal, E. Bozorgzadeh. Fast timing closure by interconnect criticality driven delay relaxation [C]// Washington, DC, USA.. ICCAD'05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, 2005 : 792-797.
  • 8K. SHI, G. GODWIN. Hybrid hierarchical timing closure methodology for a high performance and low power dsp[C]//New York, NY, USA: IEEE/ACM Proc. of DAC, 2005 : 850-855.
  • 9Xiong J J, He L. Full chip routing optimization with RLC crosstalk budgeting[J]. IEEE Trans on CAD of integrated circuits and systems, 2004,23 (3):366-377.
  • 10Hui Kong,Tan Yan,Wong M D F.Optimal simultaneous pin as-signment and escape routing for dense PCBs[C]//Design Auto-mation Conference(ASP-DAC).Taipei,China:IEEE Press,2010:275-280.

引证文献2

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部