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符号模拟 被引量:2

Symbolic Simulation
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摘要 符号模拟将模拟验证从布尔值扩展到符号领域,是集成电路验证行业中的重要分支。符号方法将符号值加到待验证电路的基本输入端,依次计算每个结点的布尔函数,直到在电路的输出端得到由这些初始符号变量组成的布尔表达式,并判断其是否具有所期望的特征。该文介绍了符号模拟的发展过程、基本技术及其所面临的BDD爆炸问题,并对消除该问题的两种技术:近似值法和参数方法,进行了讨论。介绍了具有一定自动机处理能力的符号轨迹评价方法。 Symbolic simulator assigns symbolic variables to the inputs of both specification and implementation, propagates those to the outputs, builds the symbolic expressions for both circuits, and checks the corresponding signals. The paper introduces the history, basic technology, and the drawback of BDD blowup of symbolic simulation. The two techniques, approximate value method and parametric method, which are used to eliminate the BDD blowup problem, and symbolic trajectory evaluation(STE) is also introduced.
出处 《计算机工程》 CAS CSCD 北大核心 2007年第20期27-29,33,共4页 Computer Engineering
基金 国家自然科学基金资助项目(60373113) 国家"973"计划基金资助项目(2004CB318000)
关键词 符号模拟 近似值 参数方法 符号轨迹评价方法 symbolic simulation approximate value parametric method symbolic trajectory evaluation
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参考文献6

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同被引文献25

  • 1刘卓军,吴尽昭.集成电路验证技术[J].中国基础科学,2007(3):11-14. 被引量:3
  • 2苏开乐,骆翔宇,吕关锋.符号化模型检测CTL[J].计算机学报,2005,28(11):1798-1806. 被引量:24
  • 3Anand L, Souza D, Hsiao M S. Error Diagnosis of Sequential Circuits Using Region - Based Model[A]. Proceedings of IEEE VLSI Design Conference[C]. 2001 : 103 - 108.
  • 4Shi- Yu Huang. Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation[A]. 20th IEEE VLSI Test Symposium[C]. 2002.
  • 5Boppana V,Mukherjee R,Jain J,et al. Multiple Error Diagnosis Based on Xlists[A]. Proceedings of Design Automation Conference[C]. 1999: 100 - 110.
  • 6Nandini Sridhar, Hsiao M S. On Efficient Error Diagnosis of Digital Circuits[A]. Proceedings of International Test Conference[C]. 2001 : 678 - 687.
  • 7Li Guanghui,Shao Ming, Li Xiaowei. Design Error Diagnosis Based on Verification Techniques [A]. Proceedings of the 12th Asian Test Symposium[C]. 2003:7 081 - 7 735.
  • 8Jain A, Boppana V, Mukherjee R, et al. Verification and Diagnosis in the Presence of Unknowns[A]. 18th VLSI Test Symposium[C]. 2000 : 263 - 269.
  • 9Smith A,Veneris A,Viglas A. Design Diagnosis Using Boo- lean Satisfiability[A]. ASPDAC[C]. 2004:218- 223.
  • 10Prasad M R,Biere A,Gupta A. A Survey of Rencent Advances in SAT - based Formal Verification[J]. Int'l Journal on Software Tools for Technology Transfer ,2005,7(2) :.156 - 173.

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