并行CISC指令译码器的设计与实现

Design and implementation of parallel CISC instruction decoder

针对x86系列兼容微处理器串行译码速度慢、效率低的缺点,提出了一种并行译码器设计方案。该方案将整个译码过程分为长度译码和地址译码两个阶段进行流水译码,在指令不带前缀的情况下单拍完成长度译码,支持任意两条指令并行译码,提高了译码效率。其使用Verilog-HDL进行描述,SYNOPSYS-DV在SMIC CMOS0.18工艺库下进行综合。结果表明完全达到了设计要求。

The defect of serial decoder scheme in x86 series microprocessor was slow speed and low efficiency. To overcome these problems, proposed a parallel decoder scheme. Divided the whole decoder process into two stages, which were length decode and address decode. These two stages decoded instructions in pipeline mode. The length of an instruction without prefix could be figure out in one clock. Any two instructions could be decode in parallel. So, improved the efficiency of decoder. Used Verilog-HDL to describe the whole design, and used SYNOPSYS-DV to synthesize in SMIC CMOS 0. 18-library. The results reach the design specification.