一种AES算法的FPGA设计与快速实现

FPGA design and celerity implementation of AES algorithm

针对AES算法特点,提出一种适于FPGA实现的改进的快速AES算法。本方案采用轮内流水线结构和密钥并行处理,ECB操作模式,并且可在一块芯片上同时支持128、192、256bit三种密钥长度,因而在占用相对较少的逻辑资源下提高了系统吞吐率,并且极大的增强了其安全性和使用周期。通过优化的逻辑层次和时序设计,较好地解决了并行处理中的子密钥与轮函数的时序节拍与控制关系,给出了仿真图。实验结果表明该设计相比其他一些设计具有更高性能。

According to the characteristic of AES algorithm, an ameliorated fast AES algorithm which is suitable for FPGA implementation is presented. An inner-pipeline, parallel key and ECB model are adopted in this method. And it supports 128, 192, 256 bit three keys, thus it improves the throughput of the system with relatively less logic resources being occupied, and hugely boosts the security and period for use. Through the optimized design of logic arrangement and scheduling, the scheduling and control of the Subkey and Roundfunction in paraller process is solved better. The simulation chart is presented. The results show that this design has better performance compared with the other FPGA implementations of AES.