基于FPGA的片内多址I^2C总线控制器设计

A FPGA Based I^2C Bus Controller with Sub-address Strobe

介绍了I2C总线的工作原理及数据传输格式,分析了本设计在传统I2C总线控制器上的改进,由于加入了片内地址,更有利于实现系统集成,接着用自顶向下的设计方法首先给出了基于FPGA的片内多地址地址I2C总线控制器和从动器件总体架构,进行了Verilog语言的行为源描述,并给出了系统的仿真波形,仿真结果表明其能够在快速模式下很好的工作,最后通过FPGA实现。

In this paper, we propose a FPGA based high -performance I^2C bus controller with Sub -address Strobe. Multiple Sub -addresses in I^2C bus controllers will certainly benefit system integrating. We first describe the fundamentals and transmission format of I^2C bus, then we present the over- allstructure of our design using the Top -Down method. We also make behavioral level descriptions of the sub - units using Verilog HDL. The simtdation results shows that it can work well at a speed of 400K bit/s.