基于SystemC和ISS的软硬件协同验证方法

Hardware/Software Co-verification Method Based On SystemC and ISS

随着SoC的出现和发展,软硬件协同验证已经成为当前的研究热点。本文对传统的基于ISS的软硬件协同验证方法进行改进,提出了一种基于SystemC和ISS的软硬件协同验证方法。该方法使用SystemC分别对系统进行事务级、寄存器传输级的建模,在系统验证早期进行无时序的软硬件协同验证,后期进行时钟精确的软硬件协同验证,并对仿真速度进行了优化。同传统的基于ISS的软硬件协同验证方法相比,该方法保证了软硬件的并行开发,且仿真速度快、调试方便,是一种高效、高重用性的软硬件协同验证方法。

With the appearance and development of SoC, hardware/software co-verification has been a focus of current research. In this article, on the basis of traditional co-verification method based on ISS, we put forward a co-verification method based on SystemC and ISS. In this method, we model the system and co-verify hardware/software at the transaction level and RTL level with SystemC. Furthermore, we optimize the simulation techniques. Compared to traditional co-verification method based on ISS, our method insures hardware and software＇s concurrent developing, provides faster simulation and convenient debugging, and it has been proven to be a highly effective and highly reusable co-verification method.