一种单倍RAM交织器的公式推导与验证

Deduction and verification of the formula in the design of interleaver and deinterleaver using single RAM

一般的交织器都是用双倍RAM在读写控制逻辑的控制下实现乒乓读写,其优点是控制简单,缺点是占用资源大。本文在利用单倍RAM资源来实现交织和解交织方案的基础上,针对其中较复杂的读写时延关系,通过建立模型而分析归纳出最小读写时延公式,最后通过FPGA的设计实例验证了该公式的正确性。实践证明推导的公式使该单倍RAM交织器的设计过程得以简化,具有很好的实用价值。

Common interleaver uses two pieces of RAM to read and write by turns in the management of the logic control unit. The advantage is that it can be easily controlled, while the disadvantage is that it takes up too much resource. Based on a scheme of interleaver and deinterleaver with single RAM which is studied and confronted with the complex time-delay relationship, a minimum time-delay formula is then deduced after modeling. At last, the formula is proved to be right as a design and the application of it was realized successfully on the FPGA device. The formula can help to simplify the design of the interleaver which uses single RAM and has good usage in practice.