期刊文献+

系统异构冗余容错设计研究 被引量:9

Research on redundancy and tolerance of system with different structures
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摘要 提出了一种新的三模异构冗余自修复系统的设计方法,设计出了异构评价函数。利用演化硬件具有自适应与自修复的功能,实现了具有N模冗余特性的三模冗余电路。首先,利用遗传算法进化出3个原始功能电路;然后,每进化出一个具有相同功能的电路进行一次非相似度评价,选择出非相似度最大的3个电路保留,并进行应用。当3个异构电路中有一个出错后,对故障电路屏蔽,可进化修复该出错电路,并重新投入运行。从而大大地提高了容错性能,且具有体积小、成本低、功耗小、不影响系统正常运行等优点。利用现场可编程逻辑门阵列(FPGA)对二位比较器进行容错设计验证,分析比较了非相似度评价在异构设计中的作用与影响,实验结果证明了新方法的可行性和电路的高度可靠性。 A new design method of triple-modular self-repairing redundant fault-tolerant circuits with different structures is proposed. A new function is designed to measure the difference of structures. Using the self-design and self-repair of evolvable hardware, triple-modular redundancy is implemented that has the same capability with the N-modular redundancy. Firstly, genetic algorithm is used to generate circuits. When the generated circuits' totality is three or more, the difference function will be used to evaluate them and three best circuits are reserved. They will be applied in the system when the stop condition is satisfied. If any fault is occurred accidentally, the fault circuit will be separated from system. After it is repaired and inserted again, the system will have the same fault-tolerant capability with the original. So it improves the fault-tolerant capability, and has advantages of small volume, low cost, low power and didn' t affect the system' s function. The effect is validated by the 2 bits comparator with FPGA. The effect of the difference function is analyzed in the design process. The experimental results prove that the new method is feasible and the designed system is reliable rarely.
出处 《传感器与微系统》 CSCD 北大核心 2007年第10期25-28,共4页 Transducer and Microsystem Technologies
基金 国家自然科学基金资助项目(60374008 90505013) 航空科学基金资助项目(2006ZD52044 04I52068)
关键词 演化硬件 在线进化 容错 三模冗余 异构 自修复 evolvable hardware evolution on line fault tolerance triple-modular redundancy different structure self-repair
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参考文献15

  • 1Kim H, Jeon H J, Lee K, et al. The design and evaluation of all voting triple modular redundancy system [ C ]//Proc of the 2002 Reliability and Maintainability Symposium, IEEE, 2002 : 439-444.
  • 2徐志根,王长林.三模冗余结构微机联锁系统的安全度分析[J].西南交通大学学报,1999,34(6):713-717. 被引量:3
  • 3朱明程,温粤.FPGA动态可重构数字电路容错系统的研究[J].东南大学学报(自然科学版),2000,30(4):138-142. 被引量:19
  • 4Jiang Jianhui, Shi Hongbao, Min Yinghua, et al. A novel NMR structure with concurrent output error location capability [ C ]// Proc of the 1999 Dependable Computing, IEEE, 1999:32-39.
  • 5Chen Hanfei,Dong Jingxiang,Sun Youxian. A new task model for COTS-based N-modular redundant systems[ C ]//Proc of the 2004 Intelligent Control and Automation, IEEE, Hangzhou, 2004: 4011-4015.
  • 6Tyrrell A M,Hollingworth G,Smith S L. Evolutionary strategies and intrinsic fault tolerance [ C ]//Proceedings of the 3 rd NASA/DoD Evolvable Hardware Workshop,2001:98-106.
  • 7Yao X, Higuichi T. Promises and challenges of evolvable hardware[ J]. IEEE Transactions on Systems, Man and Cybernetics Part C : Applications and Reviews ,1999,29 (1):87-97.
  • 8Lee J, Sitte J. Gate-level morphogenetic evolvable hardware for scalability and adaptation on FPGAs[ C ]//Proc of the First NASA/ESA Conference on Adaptive Hardware and Systems,2006 :145 -152.
  • 9Karunya B, Uma R. Functional level implementation of evolvable hardware using genetic algorithms [ C ]//Proc of Mixed Design of Integrated Circuits and System,2006:671-674.
  • 10Zhang Yang,Smith S L,Tyrrell A M. Digital circuit design using intrinsic evolvable hardware[ C ]////Proceedings of the 6rd NASA/ DoD Evolvable Hardware Workshop ,2004:55 -62.

二级参考文献28

  • 1赵志熙.车站信号控制系统[M].北京:中国铁道出版社,1992.178-185.
  • 2胡谋,计算机容错技术,1995年,200页
  • 3赵志熙,微机联锁系统技术,1995年,47页
  • 4赵志熙,车站信号控制系统,1992年,178页
  • 5袁由光,容错与避错技术及其应用,1992年,153页
  • 6Fernanda Lima,Luigi Carro,Ricardo Reis.Designing Fault Tolerant Systems Into SRAM-based FPGAs.Design Automation Conference,Proceedings,2003:650-655.
  • 7Glenn H Chapman,B Dufort.Using Laser Defect Avoidance to Built Large-area FPGAs.IEEE Test Design Comput,1998.
  • 8Miron Abramovici,Charles Stroud.BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs.International Test Conference,Proceedings,2000:785-794.
  • 9Charles Stroud,Miron Abramovici.On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.On-Line Testing Workshop,Proceedings,2001:27-33.
  • 10John Lach,William H mangione-Smith.Enhanced FPGA Reliability Through Efficient Run-Time Reconfiguration.IEEE Transactions on Rellability,2000,49(3).

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引证文献9

二级引证文献18

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