一款异步256kB SRAM的设计

Design of 256-kbit Asynchronous SRAM

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。

The design of a 256k bit SRAM is presented in this paper. This SRAM is achieved by using six transistor CMOS memory cell, latched sense amplifier, and ATD circuit. The SRAM is achieved by 0.5μm CMOS technology. The access time of SRAM is 12ns.