期刊文献+

IP复用的FSPLC微处理器SOC设计 被引量:1

Design of FSPLC Microprocessor based on IP Resume
下载PDF
导出
摘要 设计了一种专用PLC微处理器SOC模块FSPLC,基于IP核复用方法和SOC技术复用第三方AVRAT90S1200IP核基础上集成了自行设计的LP、BP、MBI、CBI、BBI等模块,以AlteraNiosII开发板作为验证平台对实际的PLC应用程序做了可行性验证,FSPLC具有快速处理PLC梯形图程序、快速处理指令表语句中复杂的嵌套逻辑运算、PLC之间CAN总线通讯等优点。 The paper designs the special PLC microprocessor SOC module FSPLC,integrated such the modules as LP , BP, MBI , CBI, BBI designed by oneself ,etc. on the basis of resuming the third-party AVR AT90S1200 IP core. The Ahera NiosII development board is taken as the verification flafform to make feasible verification for the actual PLC application program, FSPLC can rapidly deal with the PLC LD program and the complicated nested logic operation, carry out CAN bus communication among the PLCs and so on.
出处 《微电子学与计算机》 CSCD 北大核心 2007年第11期110-113,共4页 Microelectronics & Computer
关键词 AVR SOC FSPLC LP IP核复用 微处理器 AVR SOC FSPLC LP IP core resume microprocessor
  • 相关文献

参考文献6

二级参考文献15

  • 1Stephen B.Furber. VLSI RISC Architecture and Organization, marcel Dekker Inc. 1989:5~22.
  • 2Pigue C,M asgonty J M. Low-power design of 8-bit embedded CoolRisc micro-controller cores [J]. IEEE J SolidState Circuits, 1997; 32 (7): 1067.
  • 3ATMEL Embedded RISC Microcontroller Core [Z].Atmel Corp.
  • 4Dolle M, Schlett M. A cost-effective RISC/DSP microprocessor for embedded systems [J]. IEEE Micro, 1995; 10: 32.
  • 5Kurup P, Abbasi T. Logic synthesis using synopsis[M] Kuwer Academic Publishers, 1997.
  • 6Grant Martin. Design methodologies for system level IP Design. Automation and Test in Europe, 1998, Proceedings.
  • 7Motorola Co..M.Core Programmer's Reference manual. 1997.
  • 8VISA.http://www.vsi.org.
  • 9.CDK用户手册[Z].苏州国芯科技有限公司,2002..
  • 10Gajski D D,Proc the ASPDAC Design Automation Conference Asia and South Pacific,2000年,37页

共引文献17

同被引文献4

  • 1Xu Meihua, Ran Feng, Chen Zhangjin, et al. IP core design of PLC microprocessor with boolean module [C]// Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, Shang- hai: IEEE, 2005 : 1- 5.
  • 2Kyenonghoon Koo, Gab Seon Rho, Wook Hyun Kwon, et al. Architeetual design of a RISC processor for pro- grammable logic controllers [J]. Preprint submitted to Elsevier preprint, 1998,44(5) :311-325.
  • 3Gab SeonRho, Kyeonoghoon Koo, Naehyuc Chang, et al. Implementation of a RISC microprocessor for pro- grammable logic controllers[J]. Elsevier Science B V, Microprocessors and Microsystems, 1995, 9 (10):599 -608.
  • 4张英武,袁国顺.32位嵌入式RISC处理器的设计与实现[J].微电子学与计算机,2008,25(6):14-17. 被引量:10

引证文献1

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部