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用于PDP扫描驱动芯片的低成本VDMOS及其兼容工艺(英文) 被引量:2

Cost-Effective VDMOS and Compatible Process for PDP Scan-Driver IC
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摘要 给出了采用硅外延BCD工艺路线制造的低成本的VDMOS设计,纵向上有效利用17μm厚度的外延层,横向上得到的VDMOS元胞面积为324μm2,工艺上简化为18次光刻,兼容了标准CMOS、双极管和高压p-LDMOS等器件.VDMOS测试管的耐压超过200V,集成于64路170 PDP扫描驱动芯片功率输出部分,通过了LG-model-42v6的PDP上联机验证. A VDMOS integrated in a 170V scan-driver chip of a plasma display panel (PDP) is described,which is based on epitaxial bipolar-CMOS-DMOS (BCD) technology. Some key considerations and parameters of the design are discussed. The thickness of epitaxial layer is 17μm, the area of a single VDMOS structure cell is 324μm^2, and only 18 photoetching steps are needed in the development process. It is also compatible with standard CMOS, bipo- lar,and p-LDMOS devices. The breakdown voltage of VDMOS in the process control module (PCM) is more than 200V. Five kinds of VDMOS modules are integrated in 64 channel PDP scan-driver IC, and on-line system verifica- tion is done on a LG-model-42v6 PDP.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第11期1679-1684,共6页 半导体学报(英文版)
基金 国家高技术研究发展计划(批准号:2003AA1Z1410) 西安科技发展计划(批准号:ZX04003)资助项目~~
关键词 PDP VDMOS BCD工艺 低成本 元胞结构 PDP VDMOS BCD process cost-effective structure cell
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