A High Voltage BCD Process Using Thin Epitaxial Technology

基于薄外延技术的高压BCD兼容工艺(英文)

A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.

针对高压应用领域,开发了一种基于薄外延技术的高压BCD兼容工艺,实现了900V高压双RESURF LD-MOS与低压CMOS,BJT器件的单片集成.与传统厚外延技术相比,工艺中n型外延层的厚度减小为9μm,因此形成pn结对通隔离的扩散处理时间被极大减小,结隔离有更小的横向扩散,节约了芯片面积,并改善了工艺的兼容性.应用此单层多晶、单层金属高压BCD兼容工艺,成功研制出一种基于耦合式电平位移结构的高压半桥栅极驱动电路,电路高端浮动偏置电压为880V.