用CPLD实现交换电路优化设计

Optimization Design of Switch Circuit with CPLD

介绍了一种使用CPLD对时隙交换电路优化的设计方法。早期的交换电路逻辑复杂、稳定性差。以交换电路为例,描述了CPLD的设计开发环境;使用CPLD进行交换电路优化设计的基本工作流程;开发设计过程中一些需要注意的问题等。通过数据对比,CPLD优化后的交换电路性能稳定、成本低廉。该方法也可用于一般CPLD的开发设计工作。

This paper introduces a method for optimization design of time switch with CPLD. The logics are complicated and have poor stability in early switch circuit. This paper illustrates the design environment of CPLD, basic work flow of optimization design with CPLD, and some issues necessary for consideration in CPLD design etc. Through comparation with early switch circuit, it is found the fact that the new switch circuit after optimization design with CPLD is stable and inexpensive. This method is also suitable for other common developments and designs of CPLD.