Viterbi译码的FPGA免回溯实现

A Implementation of a Non-backtracking Viterbi Decoding Algorithm in FPGA

卷积码在多种通信领域中广泛应用,Viterbi译码是对卷积码的一种最大似然译码算法。随着卷积码约束度的增加,并行维特比译码所需的硬件资源呈指数增长,限制其硬件实现。介绍了一种串行译码结构的FPGA实现方案,在保证性能译码的前提下有效地节省资源。同时提出了充分利用FPGA的RAM存储单元的免回溯Viterbi解码实现算法,减少了译码时延,这种算法在串行和并行译码中都可以应用。

Convolutional coding has been widely used in many communication fields, and Viterbi decoding algorithm is a maximum likelihood algorithm for the convolutional code. The hardware resource required for parallel Viterbi decoding shows an exponential increase with the increase of constraint length of convolutional code, which limits its hardware implementation. In this paper, a FPGA implementation of a serial Viterbi decoding architecture is presented, which saves hardware resource without performance deterioration. Meanwhile, a non-backtracking solution of Viterbi decoding algorithm using the RAM units of FPGA is provided in the paper. The solution can reduce the delay of decoding, and can be implemented in both serial decoding and parallel decoding.