最小正交误差Walsh序列信号源的FPGA实现

FPGA Implementation of Walsh Sequences Generator of the Least Orthogonal Error

针对Walsh函数序列生成过程中的正交误差问题,选择利用复制理论产生Walsh序列,在Walsh序列生成过程中建立保证各路Walsh序列延时时间相等的仿真模型。模型建立原理是每个触发器产生每路Walsh序列信号,并将触发器设置成同步工作从而实现最小正交误差。对整个设计过程用Verilog HDL数字描述语言进行编程,并在Quartus II平台进行后仿真,后仿真结果和理论分析相一致,最后在FPGA上实现,为工程应用提供多位Walsh正交序列的生成。

To solve the orthogonal error problem when generating walsh sequences,firstly,they are generated in signal copy theory.Then,a simulation model,which ensures that all of walsh sequences output from each channel would had the same delay time,is designed.The principle of the model was that each channel of walsh sequence is generated via each trigger.And the triggers are designed working in synchronization.Therefore,in theory,the generated walsh sequences have the least orthogonal error.The whole design is programmed in the verilog hardware description language.Next,the program was simulated in functionality and timing with Quartus II software.The simulation result in timing is consistent with the one analyzed in theory.The generator was ultimately implemented in FPGA.This design is helpful for the generation of Walsh sequences in engineering applications.