摘要
A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.
A novel clock structure of a low-power 16-bit very large instruction word （VLIW） digital signal proces- sor （DSP） was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch ＆. decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was im- plemented following the Synopsys back-end flow under TSMC （Taiwan Silicon manufacture corporation） 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm × 2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7 % circuit is active simultaneously in average, compared to its non-gating counterparts.
基金
The Research Project of China Military Department (No6130325)
关键词
逻辑信号处理
时钟机械
逻辑设计
图象分布
digital signal processor （DSP）
deterministic clock gating （DCG）
distributed and early clock gating
low power design
pipeline
