基于各种快速Spice仿真器的Post-Layout寄生效应验证

Post-Layout Parasitic Verification Methodology Based on Fast-Spice Simulator

现在的深亚微米工艺使用复杂的多层金属结构与先进电介质材料,随着工艺的进步,集成电路的器件尺寸越来越小,金属互连线做得越来越细,金属互连产生的寄生效应对电路性能的影响也越来越明显,各种各样的问题譬如由耦合电容产生了串扰噪声和延迟,IR drop引起的电压降,高电流密度引起的电迁移效应,以及混合信号设计中DC-path泄漏已经成为非常普遍的问题。对于整个芯片,在post-layout仿真时加上提取的寄生参数,有助于在设计中精确地分析每个寄生效应。快速Spice仿真器具有大的数据处理的容量和高的处理效率,因此这种仿真流程在设计中已经被广泛地应用。讨论如何在各种模式的仿真器(如UltraSim,NanoSim和HSIM)中选择合适的仿真器来进行post-layout仿真,以及不同的选择会有什么样不同的结果,另外还将对一些post-layout仿真结果进行分析。

Current sub - 100 nanometer processes employ complex multi - layer metallization structures with advanced dielectric materials. Closely- spaced thin, tall metal interconnects lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross - talk due to coupling capacitances. IR drop effects in the low power supply operating regimes,high current density causing electro- migration in narrow interconnect structures ;and DC path leakage currents are becoming very common effects in recent mixed- signal designs. Full chip, post -layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. For the relevant process corners and perform the analysis, fast -Spice simulator- based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper we discuss various options available for designers using fast - Spice simulators （e. g. UltraSim, NanoSim,and HSIM） for postlayout simulations,and how these options affect the end results. A few examples of post - layout simulations carried out on designs will be discussed.