高速基带匹配滤波器的FPGA实现及验证

FPGA Implementation and Verification of High Speed Baseband Matching Filter

根据SDH数字微波通信系统高阶QAM解调器的设计要求,针对数字化基带滤波的信号处理特点,提出一套高速匹配滤波器的FPGA实现方案。首先基于窗函数设计法,完成了滤波器的软件设计和仿真;然后基于QuartusⅡ6.0开发平台,采用并行流水结构和Verilog HDL语言参数化设计法实现滤波器FPGA设计;最后结合QuartusⅡ和Matlab,从时域和频域验证滤波器性能。实践表明此方法设计的滤波器效率高、方便调试,具有较好的重用性和可移植性。

Aimed at the signal processing characteristics of digitally -implemented baseband filter, putting forward a design project of FPGA implementation of high speed matching filter for high - order QAM demodulator in SDH digital microwave communication system. First, Based on the windows function design method, completed the software design and simulation of the filter. Then,based on the flat of Quartus Ⅱ 6.0 ,used parallel pipelining structure and the parameter design method of the Verilog HDI.,implemented FPGA design of the filter. At last,connected Quartus Ⅱ and Matlah,ingeniously verified this filter from time field and frequency field. Practice proves that the filter is high -efficiency, facilitates dehugging and can be reused or replanted easily.