基于FPGA的多路E1信道的MPEG-2码流传输

Transmission of MPEG-2 Data through Multiple E1 Based on FPGA

阐述了多E1信道的复用、反向复用技术,并由此设计出了一种基于现场可编程门阵列(FPGA)的MPEG-2码流的多E1信道复用器、反向复用器电路。分析了FPGA具体实现过程中的一些常见问题,以及传输路由引起的多信道之间的信道时延差对接收端数据复用的影响。该设计实现了MPEG-2码流、控制码数据在多路E1信道中的透明传输,适配FPGA电路内置帧发生器和n(n=2,3,4)倍2.048MHz时钟发生器。

The paper explains the technology of multiplexer and reverse multiplexer, introduces a method of using FPGA to design the multiplexer and reverse multiplexer transmitting MPEG - 2 data through multiple E1. It analyzes some problems appearing in the process of realizing the circuit based on FPGA and the effect brought by the transport delay between the channels.The design implements the transparent transmission of MPEG- 2 data and control data through multiple E1. The FPGA circuit contains the frame generator and the clock generator of n（ n = 2,3,4） times 2048 kHz.