摘要
讨论了基于SRAM技术的可编程逻辑器件提供的PLL和全局时钟网络对时钟操作的解决方案。针对Altera公司的Cyclone EP1C6系列芯片,讨论了输出频率与参考频率的关系。介绍了PLL的功能实现和工作模式,并以基于FPGA的DDR控制器中的时钟设计为例,介绍了PLL在实际应用中的设计方法和步骤。最后讨论了在设计时应该注意的问题和解决办法。
The paper discusses the clock operation solution by phase locked loops （PLLs） and global clock network offered by the programmable logic device based on the SRAM technology. For the Cyclone EP1 C6 chip series of Ahera, the relationship between output frequency and reference frequency is discussed.The function realization and operation mode of PLL are introduced .Then the methods and steps in the practical applications of phase locked loops （PLLs） are introduced with the clock design of DDR SDRAM controller based on programmable gates array devices as an example. The problems in the design are discussed and their solutions are given.
出处
《无线电工程》
2007年第9期62-64,共3页
Radio Engineering
关键词
PLL
占空比
全局时钟网络
可编程
phase-locked loop
duty cycle
global clock network
programmable
