叠层片式ZnO压敏电阻的微观结构研究

The microstructure study of multilayer chip ZnO varistors

通过光学显微镜、扫描电镜观察及能谱分析等方法，分析研究了叠层片式压敏电阻器（MLV,mutilayer varistor）的微观结构．实验结果表明，在半成品叠层片式压敏电阻器的微观结构中ZnO晶粒较小且不均匀，结构较疏松，强度差．而成品由于进行了低温液相烧结，其微观结构则为较规则的ZnO晶粒，晶粒变大尺寸较为均匀，致密度明显提高．由于在陶瓷叠片上内电极浆料分布不均匀或电极印刷的原因，经过烧结后个别地方可能出现内电极层的缺损，以至观察到的内电极是断续的。同时观察到空洞可影响到内电极扣外电极的连接，以及电极变形等现象。这些缺陷结构的形成与叠层片式压敏电阻器的制作工艺有关．

This paper studies the microstructures of multilayer chip varistors by using optical microscope （OM）, scanning electron microscope （SEM） and the EDAX analysis. The results show that the semi-finished multilayer chip varistors have the microstructures consisting of the size varied ZnO grains and small spinel particles. The structure is relatively loose, easy to crack. The finished samples, as results of low-temperature liquid phase sintering, have microstructures of the larger and more uniform grains, the densification has also been improved significantly. As the inner electrode ink printing on the ceramic coating is uneven or the processing is not properly, after sintering shrinking, some small regions may loss the electrode metal （Ag）, so the observed inner electrodes are intermittent at these regions. It has been observed that in some combined regions between the inner electrodes and outer electrodes are not connected due to the existing of the pores. Meanwhile, the electrode deformation can also be observed. These defects will affect the properties of the multilayer chip varistors.