摘要
SDH中C_4映射的码速调整电路是SDH各映射中工作速度最高的。在用专用集成电路实现时，对集成电路的工艺和功耗都提出了很高的要求。本文提出了采用并行处理实现正码速调整的新方法，有效地解决了采用常规串行码速调整电路时工作频率过高的问题，并且利用FPGA对并行码速调整方法进行了实验研究，得出的测试结果优于国际市场上的一些产品。
The mapping of C_4 has the highest system frequency in all the Bit Rate Justifications of SDH. This demands highly on the technology and power consumption in the ASIC design. This paper puts forward a new technique of Positive Justification with Parralell Processing and solves the problem. We have implemented the design with FPGAs. The paper ends with the jitter test results, which are better than some commercial products in the international market.
出处
《高技术通讯》
EI
CAS
CSCD
1997年第2期1-5,共5页
Chinese High Technology Letters
基金
863计划
