基于FPGA的虚拟逻辑分析仪设计

Design of Virtual Logic Analyzer Based on FPGA

逻辑分析仪用于涉及大量信号或复杂的触发器要求的数字测量,但是以往的独立式逻辑分析仪不仅结构复杂,而且价格昂贵。介绍了一种基于FPGA的虚拟逻辑分析仪的工作原理和设计方法,重点阐述了虚拟逻辑分析仪的硬件电路设计和软件设计部分。

Logic Analyzer is used for testing digital information in the system refer to mass signals or complicated trigger request, but the independent Logic Analyzer is not only expensive,but also its structure is complexThis paper introduces the working principle and design methods of Virtual Logic Analyzer based on FPGA,the design of circuit hardware and software was simplified.