摘要
本文给出了一种采用自偏置技术的低抖动延迟锁相环,可应用于高频时钟产生电路。分析了环路带宽和工作频率的关系,并给出了各模块具体的电路设计。在0.35μm标准CMOS工艺、3.3V工作电压下进行了模拟仿真,在100MHz的参考输入频率下,DLL锁定时间为1μs,VCDL输出的相位抖动为17μs,倍频器输出的相位抖动为90μs。
In this paper, a low-jitter process-independent DLL（delay locked loop） based on self-biased techniques is presented. It can be applied in high frequency clock generator. An analysis on the relationship between the loop bandwidth and the operation frequency and the circuit design of DLL is described. Since the 0.35um CMOS technology and 3.3V voltage supply, the locking time is approximately 1μs, the peak-to-peak jitter of the VCDL output and FM output are ps and ps with 100 MHz input.
出处
《微计算机信息》
北大核心
2007年第35期270-272,共3页
Control & Automation
基金
上海市科委国际合作发展基金资助(055207041)
