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FPGA测试中故障屏蔽现象的分析和研究 被引量:4

Research on Fault Mask in the Test of FPGA
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摘要 通过对基于SRAM结构的FPGA测试方法进行分析和研究,提出了FPGA测试中的故障屏蔽现象,并给出该现象的产生原因和判断条件,在此基础上,进一步提出相应的解决办法和建议,以避免或减少故障屏蔽现象的出现,提高测试FPGA的故障覆盖率. Field Programmable Gate Arrays (FPGAs)are widely used in the hardware implementation of circuit design. Detecting the faults of FPGAs is very important. This paper presented the problem of fault mask in the test of FPGA, and focused its research on the generating reasons and conditions of fault mask. Finally, the solutions and suggestions are given to reduce its appearance and to improve the fault coverage of FPGA test.
出处 《测试技术学报》 2007年第6期557-561,共5页 Journal of Test and Measurement Technology
关键词 FPGA测试 测试方法 故障屏蔽 FPGA testing test method masking of faults
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参考文献11

  • 1Huang W K,Meyer F J,Lombardi F.Array-based testing of FPGAs:architecture and complexity[C].Proc IEEE Innovative Systems in Silicon Conf.USA.1996:249-258.
  • 2Huang W K,Lombardi F.An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays[C].14th IEEE VLSI Test Symposium,Princeton.NJ,USA,May 1996:450-455.
  • 3Huang W K,Meyer F J,Lombardi F.A XOR-Tree Based Approach for Testing and Diagnosing Configur-able FPGA s[C].6th ATS.Japan.1997:248-253.
  • 4Huang W K,Lombardi F.Multiple Fault Detection in Logic Resources of FPGAs[C].International Sympo-sium on Defect and Fault Tolerance in VLSI Systems.France.1997:183-191.
  • 5Huang W K,Meyer F J,Lombardi F.An approach for detecting multiple faulty FPGA logic blocks[J].IEEE Transactions On Computers,2000(1):48-54.
  • 6Renovell M,Portal J M,Figueras J,et al.An approach to minimize the test configuration for the logic cells of the xilinx XC4000 FPGAs family[J].Journal of Electronic Testing:Theory and Applications,2000(3):289-299.
  • 7Goyal S,Choudhury Mi.Multiple Fault Testing of Logic Resources of SRAM -Based FPGA s[C].Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.India.,2005:742-747.
  • 8Doumar A,Hideo I.Detecting,Diagnosing,and tolerating faults in SRAM-based field programmable gate arrays:a survey[J].IEEE Transactions On Very Large Scale Integration(VLSI) Systems,2003,11 (3):386-405.
  • 9黄维康.FPGA的测试[J].计算机辅助设计与图形学学报,2000,12(5):396-400. 被引量:13
  • 10Inoue T,Fujiwara H,Michinishi H,et al.Universal test complexity of field-programmable gate arrays[C].Proc 4th IEEE Asian Test Symp.Japan.1995:259-265.

二级参考文献7

  • 1Huang W K,Proceedings ATS’ 97,Akia,Japan,1997年,248页
  • 2Huang W K,Proceedings IEEEConference on Innovative Systems in Silicon,1997年,249页
  • 3Huang W K,Proceedings IEEEInternational Symposium on Defect and Fault Tolerance inVL SI Sy,1997年,186页
  • 4Huang W K,Proceedings 14th IEEE VLSI Test Symposium,1996年,331页
  • 5Huang W K,Proceedings 14th IEEE VLSI Test Symposium,1996年,450页
  • 6Liu T,Proceedings ACMInternational Symposium on FPGAs,1995年,125页
  • 7Chan P K,Proceedings IEEE Workshop onF PGAs for Custom Computing Machines,1993年,152页

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同被引文献41

引证文献4

二级引证文献23

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